YH001 PCIe Accelerator Card 48GB

YH YH001 is a next-generation AI accelerator on RISC-V architecture with TPU-like computation organization and dual systolic arrays.

Features 48 GB HBM3e (1000 GB/s). Up to 8 YH001 cards per server. YHLink interconnect supports two configurations: TP4 — two groups of 4 cards with full mesh connectivity, or TP8 — one group of 8 cards in ring topology.

The proprietary YHLink is positioned as an alternative to NVIDIA NVLink for large-scale cluster deployment and supports In-Network Computing — executing operations directly within the network to reduce latency and offload compute from the chips.

Blocked FP8 support for efficient LLM training.

Complete CUDA independence: native PyTorch and TensorFlow.

Application scenarios

LLM training and inference with TP4/TP8 (YHLink) topologies.
CUDA-independent AI cluster deployment with YHLink.
Distributed training with In-Network Computing.
Scalable AI infrastructures.

Product overview

Purpose-built accelerator for enterprise AI workloads

Designed for dense inference, model adaptation, and private AI infrastructure where predictable availability, localized supply, and software compatibility are critical.

Architecture

TPU Архитектура

Memory & Performance

High-bandwidth memory profile for AI inference and training.

VRAM capacity48

Memory typeHBM3e

Memory bandwidth1000

Interconnect typeYHLink

Interconnect speed600

Architecture

Compute architecture and software execution model.

ArchitectureTPU Архитектура

Compute units-

Power & Thermal

Data center integration requirements.

Thermal design power-

CoolingПассивное

Form factorPCIe Card

Pixel Rate-

Texture Rate-

Benchmarks

Peak theoretical compute for common AI precisions.

FP64

INT4 TOPS 1024

FP32

FP16

TF32

BF16 Tensor

256

FP8 Tensor

512

INT8 Tensor

512

Compatibility

Interfaces, frameworks, and deployment environment.

PCIe interfacePCIe 5.0x16

Video encoding-

Video decoding-

Pricing

On request

Volume pricing available for cluster deployments and pilot batches.

Documentation