Overview of the MetaX C500 Server 512GB

The MetaX C500 Server 512GB is the flagship GPGPU platform based on eight accelerators of the company’s proprietary architecture. The configuration is a dense 4U computer that combines two Intel Xeon Gold processors, 1 TB of DDR5 RAM, and eight MetaX C500 accelerators. The total capacity of the HBM2e video memory is 512 GB, which opens up opportunities for working with generative DeepSeek-R1 or LLaMA-70B scale models in their entirety, without complex splitting of parameters between nodes.

In the context of the transformation of the global high-performance computing market and the departure of key Western vendors, the issue of ensuring technological sovereignty is becoming critical for Russian corporations, government agencies and research centers. The shortage of NVIDIA graphics accelerators has pushed the industry to look for alternative ways to develop AI infrastructure. One of the most mature responses to this challenge was the introduction of server hardware from the Chinese developer MetaX Integrated Circuits.

Technical Specifications of MetaX C500 Server 512GB

Specifications of one MetaX C500 accelerator (PCIe version):

Graphics Processor:

Architecture: MXMACA (MetaX Memory Access and Compute Architecture);

Computing units: AP (Arithmetic Processors) organized into a matrix;

Process technology: 7 nm.

Performance (per card):

FP32 (vector): ~18 — 19 TFLOPS;

FP16/BF16 (matrix): 240 TFLOPS (with sparsity/structural sparsity, the value can reach 280 TFLOPS);

INT8: 512 TOPS (according to some specifications, peak values reach 560 TOPS).

Memory:

Memory Type: HBM2e;

VRAM Capacity: 64 GB;

Bandwidth: 440 — 460 GB/s;

Bus bit rate: 4096 bits.

Interfaces and connectivity:

Host Interface: PCI Express 4.0 x16;

Card-to-card interconnect: MetaXLink (proprietary). Speeds of up to 256 GB/s for connecting 2-cards and up to 384 GB/s for 4-cards via PCIe. In OAM format (C550) — up to 896 GB/s with a full connection of eight cards.

Energy consumption and cooling:

TDP (heat package): 350W;

Cooling: Passive (requires server chassis fans) or optional liquid cooling;

Form factor: Dual-slot PCIe expansion card.

Summary characteristics of the MetaX C500 Server 512GB (8x GPU):

Total FP16 performance: ~1920 TFLOPS (8×240 TFLOPS);

Total INT8 performance: ~4096 TOPS (8 × 512 TOPS);

Central processor: 2× Intel Xeon Gold 6530 (8 cores each according to the source text, a total of 64 physical cores / 128 threads; base frequency about 2.1 GHz, Boost up to 3.2 GHz, L3 cache — 160 MB total, power limit 270 watts per CPU);

RAM: 1 TB DDR5-4800 ECC RDIMM (16 modules of 64 GB each).

Data storage system:

• Main array: 2× NVMe SSD 7.68 TB (PCIe Gen4 interface);

• System disk: 2× SATA SSD 480 GB.

Network interfaces:

• High-speed layer: 2× 400 Gbps (implemented via PCIe 5.0 switches to minimize RDMA delays);

• Control layer: 2× 25 Gbit/s SFP28.

Nutrition and physical parameters

Power supplies: 4× 2700 W (Platinum/Titanium certified), 3+1 redundancy scheme;

System power consumption: up to 5,000 watts at full load (considering the efficiency of the power supplies and the consumption of the motherboard/CPU);

Form factor: 4U rack.

Performance comparison with NVIDIA A100

To illustrate the generation gap, it is advisable to compare the technical data of the C500 with NVIDIA’s flagship of the previous generation.:

FP16: The C500 has 240 TFLOPS compared to 312 TFLOPS for the A100 80GB. Thus, the computational density of the Chinese chip reaches about 77% of the American equivalent of four years ago.

Architecture features of the MetaX C500 Server 512GB (8x GPU)

The architecture of the MetaX C500 is the result of the work of a team from AMD, which defined its engineering philosophy.

MXMACA Microarchitecture and AP computing units The GPU is based on the proprietary MXMACA architecture (MetaX Memory Access and Compute Architecture). The key building block here is not the usual Streaming Multiprocessors (SM), but proprietary Arithmetic Processors (AP).

Organization:

The AP blocks are grouped into a matrix. The interaction between them is carried out through a high-speed High-Speed Fabric bus, which provides low latency when transmitting data inside the chip.

Caching:

All AP clusters have access to a shared L2 cache pool. This solution is optimized for machine learning tasks where data coherence is important in distributed computing. The L2 cache size is 48 MB.

Tensor kernels:

Specialized matrix engines (Tensor Cores, similar to NVIDIA) are implemented inside the AP blocks, which are responsible for basic performance in FP16/BF16 and INT8 formats.

The HBM2e C500 memory subsystem uses 64 GB HBM2e memory per card. In total, 512 GB of video memory is available in the 4U format server.

An important feature is the use of HBM stacks, rather than the cheaper GDDR6/GDDR7. This allows you to work effectively with models whose parameters do not fit into a smaller memory.

The bandwidth of a single chip is about 440 — 460 GB/s. Despite the fact that this is significantly lower than the performance of modern Western flagships, this volume is sufficient for the inference of large language models without splitting them into several nodes.

The MetaXLink interconnect uses MetaXLink technology to combine multiple accelerators within a server or cluster. It replaces the NVLink standard.

Topologies:

Point-to-point direct connection modes are supported. In the PCIe configuration, the bandwidth reaches 256 GB/s (for a pair of cards) and 384 GB/s (for four). In OAM format (specialized blade servers) The data exchange rate increases to 896 GB/s when eight cards are fully connected.

Scalability:

The technology supports topologies that can be scaled from several units to dozens of GPUs in a single cluster.

Host interface and process technology

PCI Express: The cards use the PCIe 4.0 x16 interface. The lack of PCIe 5.0 support can create a bottleneck with intensive data exchange between the CPU and GPU, however, for most deep learning pipelines, where data is loaded once before an epoch, this is not a critical limitation.

Production:

The chip is manufactured according to the norms of the 7-nanometer process technology. Given China’s sanctions restrictions on the purchase of EUV lithographs (ASML), production is likely to be deployed at the facilities of SMIC (Semiconductor Manufacturing International Corporation).

Software stack as part of the architecture The hardware part is inextricably linked to the MXMACA Software Stack. Architecturally, it is designed as a mirror image of the CUDA ecosystem.:

At a low level, KMD/UMD drivers emulate the behavior of the CUDA runtime environment.

The mcDNN (cuDNN analog), mcBLAS (cuBLAS), and MCCL libraries (NCCL analog for MPI-type collective operations) allow existing frameworks to see MetaX hardware as native.

A critical architectural advantage: Full support for the Flash Attention operator. Most alternative Chinese accelerators have problems with this algorithm for optimizing attention in transformers, whereas in the C500 architecture it is implemented in hardware and software, which gives a multiple increase in speed when working with long contexts.

The evolution of the C Series (Xiyun), which includes the C500, is positioned as universal (training + inference). It was preceded by the N (Xisi) series for pure inference, and was succeeded by the later released C600 with improved crystal packaging and increased inter-card connection performance.

Thus, the C500 architecture is a mature enterprise solution, where the main focus is not on record-breaking memory bandwidth, but on a huge amount of VRAM, software compatibility with global software, and fault tolerance under long loads.

Preliminary performance assessment

The peak performance of one C500 accelerator is 240 TFLOPS in FP16/BF16 format. In the server configuration of 8 cards, the total capacity reaches 1920 TFLOPS.

Resource Utilization (MFU) and cluster stability

The most important indicator for enterprise equipment is MFU (Model FLOP Utilization) — the percentage of the theoretical peak that can be achieved on a real task. According to the manufacturer’s testing data on a cluster of 1024 cards (OAM version C550):

MFU > 65%. This is a high indicator for the industry. For comparison, when training Dense models on Western GPUs, achieving stable MFU above 50-55% is considered an excellent result due to the optimization of the Megatron-LM/DeepSpeed stack. The stated MetaX of 65% indicates a high maturity of the MCCL drivers (similar to NCCL) and the mcDNN library.

Effective training time: 98.6%. This means that the system loses only 1.4% of its time on checkpoints, diagnostics, and crash recovery.

MTTR (Mean Time To Recovery): < 15 minutes. Of these, it takes up to 5 minutes to automatically diagnose the node and up to 10 minutes to restart the task on the backup node.

Performance on specific models (DeepSeek case study)

MetaX has published a configuration matrix for launching current open-source giants:

Inference:

A single N-series card (N260, derived from the C500 architecture) is capable of running the DeepSeek-R1/V3 model (671 billion parameters) entirely due to aggressive quantization of weights. The C500 server with 512 GB of memory allows you to serve such models in Inference with Batching mode, providing high throughput of requests (tokens/sec).

Training:

The 8xC500 configuration (512 GB HBM2e) is ideal for training LLaMA-70B or Qwen-72B class models with up to 32k tokens. With an increase in the size of the model over 100 billion parameters, multiple nodes will need to be combined via MetaXLink.

Features of scaling